Experiment No.-3 (Value Added)

Aim: Synthesis and simulation of XOR and XNOR gate.

Apparatus Used:-

S.No	Items	Specification	Quantity
1	Computer set	P-4, 2GB DDR	01
2	Software (Tool)	Xilinx 10.1	01

Theory:-

XOR Gate:

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs are high. An encircled plus sign ( ) is used to show the EOR operation. 
 

XNOR Gate:

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output. The small circle represents inversion.
 

HDL Coding:

EX-OR Gate implementation:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity EXORGATE is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC);

end EXORGATE;

architecture Behavioral of EXORGATE is

begin

Y<= A XOR B;

end Behavioral;

EX-NOR Gate implementation:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity EXNORGATE is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC);

end EXNORGATE;

architecture Behavioral of EXNORGATE is

begin

Y<= A XNOR B;

end Behavioral;

Observation/ Analysis

RTL schematic of EX-OR Gate

 
 RTL schematic of EX-NOR Gate

Results:

EX-OR GATE SIMULATION

EX-NOR GATE SIMULATION

 

Experiment-AND Gate & NAND Gate

Experiment No.-2

Aim: Synthesis and simulation of AND and NAND gate

Apparatus Used:-

S.No	Items					Specification	Quantity
1	Computer set					P-4, 2GB DDR	01
2	Software (Tool)					Xilinx 10.1	01

Theory:-

AND Gate:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB

NAND Gate:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion

HDL Coding:

AND Gate implementation:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ANDGATE is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC);

end ANDGATE;

architecture Behavioral of ANDGATE is

begin

Y<= A AND B;

end Behavioral;

NAND Gate implementation:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity NANDGATE is

Port

( A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC);

end NANDGATE;

architecture Behavioral of NANDGATE is

begin

Y<= A NAND B;

end

Behavioral;

Observation/ Analysis:-

RTL schematic of AND Gate

RTL schematic of NAND Gate

Results:

AND GATE SIMULATION

NAND GATE SIMULATION